Conventional embedded memory devices are typically synchronous in nature. A synchronous design, such as a synchronous SRAM, will not generally consume current when the clock to the block is not switching. Such designs, when implemented in embedded memories, are typically implemented with a fixed word-width.
One disadvantage with such a conventional approach is that it is not as flexible as a truly asynchronous device, which can be configured to operate either asynchronously or synchronously. For example, an asynchronous SRAM can be used to implement a logic function by using the address inputs as the logic function inputs, the data output(s) as the logic function output(s), and the memory bits as a lookup table for the output values for a given set of input values.